AK8186B draft - e - 02 sep - 2012 - 1 - f eatures low phase noise pll : rms jitter < 300fs on - chip vco tunes from 1.75g hz to 2.25g hz external vco/vcxo to 5 00 mhz optional 1 differential or 2 single - ended inputs reference switch over/ holdover modes lock detect 3 pairs of 1g hz lvpecl outputs 2 pairs of 800mhz lvds outputs 8 250 mhz cmos outputs (two per lvds) serial control register interface 3.3v+/ - 5% operating voltage 2.5v - 3.3v lvpecl drive voltage operating temperature: - 40 to + 85 c package: 64 - pin leadless qfn (pb free) pin compatible with ad9516 - 3 d escription the AK8186B is a multi - output cloc k generator with sub - ps jitter performance. the on - chip vco tunes from 1.75g hz to 2.25g hz. the distribution section has three pairs of lvpecl buffers (6 outputs) and two pairs of lvds buffers (4 outputs)/eight cmos buffers (two per lvds outputs ) . the lvpecl outputs operate up to 1g hz, the lvds outputs operate up to 8 00mhz and t h e cmos outputs operate up to 250 mhz. each pair of the outpu ts has a divider. the lvpecl outputs have the division range of 1 to 32. the lvds and cmos outputs have the 1 to 1024. the AK8186B operates at 3.3v and the lvpecl outputs are supplied independently from 2.375v to 3.6v. the operating temperature range is f rom - 40 to +85 c. the part is a vailable in a 9mm 9 mm 64 - pin leadless - qfn (pb free) package. o rder ing i nformation part number marking shipping packaging package temperature range AK8186B AK8186B tape and reel 64 - pin l eadless qfn - 4 0 to 85 multi out put cl ock generator with integrated 2.0 ghz vco AK8186B p r e l i m i n a r y
AK8186B sep - 2012 draft - e - 02 - 2 - b lock d iagram figure 1 . AK8186B block diagram cp rset cs s clk sdio sdo out0 out 0 out1 out 1 out2 ou t2 out4 out4 out6 out 6 out3 out 3 out5 out 5 pd sync reset bypass status out7 out 7 refmon out8 out8 out9 out9 lvpecl lv ds/ cmos v co lf ld rset cp distribution reference ref_sel refin/ref1 refin /ref2 referen ce switchover status status divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 divide by 1 to 32 p,p+1 prescaler r divider lock detect hold a/b counter vco status ref1 ref2 n divide r phase frequency detector pll reference charge pump ldo digital logic serial control port v co divider divider 0 divider 1 divider 2 divider 3.1 divider 3. 2 divider 4 .1 divider 4 .2 divide by 2 to 6 clk clk
AK8186B draft - e - 02 sep - 2012 - 3 - table of contents features ................................ ................................ ..... - 1 - description ................................ ................................ - 1 - ordering information ................................ ............ - 1 - block diagram ................................ .......................... - 2 - pin description ................................ ......................... - 4 - pin configuration ................................ ................... - 4 - pin function ................................ ............................. - 5 - absolute maximum rat in g ................................ ..... - 7 - recommended operatin g conditions ................... - 7 - electrical character istics ................................ ...... - 7 - p ower d issipation ................................ ......................... - 7 - pll c haracteristics ................................ ....................... - 8 - c lock i nput c haracteristics ................................ ........... - 9 - c lock o utput c haracteristics ................................ ...... - 10 - t iming c haracteristics ................................ ................. - 11 - c lock o utput a dditive p hase n oise (d istribution o nly ; vco d ivider n ot u sed ) ................................ ........................ - 12 - c lock o utput p hase n oise (i nternal vco u sed ) ............ - 13 - c lock o utput a bsolute t ime j i tter (c lock g eneration u sing i nternal vco) ................................ ............................. - 14 - c lock o utput a bsolute t ime j itter (c lock g eneration u sing e xternal vcxo) ................................ .......................... - 14 - c lock o utput a dditive t ime j itter (vco d ivider n ot u sed ) .. - 15 - c lock o utput a dditive t ime j itter (vco d ivider u sed ) ... - 15 - s erial c ontrol p ort ................................ .................... - 16 - , and ................................ ................. - 17 - ld, status and refmon ................................ ........... - 17 - timing diagrams ................................ .................... - 18 - theory of operation ................................ ............. - 19 - operational configurations ............................. - 19 - internal vco and clock distribution .................... - 19 - external vco and clock distribution .................... - 20 - pll ................................ ................................ ............. - 21 - reference input ................................ ............... - 21 - reference switchover ................................ .... - 22 - r divider (reference di vider) ......................... - 22 - phase frequency detector (pfd) .................. - 23 - charge pump (cp) ................................ ............. - 23 - on - chip vco ................................ ........................ - 23 - external vco/vcxo ................................ ............. - 24 - pll external loop filter ................................ . - 24 - figure 12 example of external loop filter for the internal vco figure 13 example of external loop filter for an external vco ............................ - 24 - feedback divider (n divider) .......................... - 24 - lock detect ................................ ....................... - 26 - holdover ................................ ........................... - 28 - frequency status monitors ................................ .. - 30 - clock distribution ................................ ................ - 31 - vco divider ................................ ........................ - 31 - channel dividers for lv pecl outputs ................ - 31 - channel dividers for lvds/cmos outputs ........ - 31 - synchronizing the outputs: sync function ....... - 32 - phase offset ................................ ......................... - 32 - lvpecl outputs : out0 to out5 ....................... - 34 - lvds/cmos outputs : out6 t o out9 ............... - 34 - reset ................................ ................................ ......... - 35 - power - on reset (por) ................................ .......... - 35 - asynchronous reset by pin ...................... - 35 - soft reset by 0x00[5] ................................ ............ - 35 - power down modes ................................ .............. - 36 - chip power down by pdn pin ............................... - 36 - pll power down ................................ .................. - 36 - ref1, ref2 power down ................................ ...... - 36 - vco and clk input power down .......................... - 36 - distribution power down ................................ ..... - 36 - individual clock output power do wn (out0 to out9) - 37 - serial control port ................................ .............. - 38 - serial control port pin descriptions ......... - 38 - general description of serial control port - 38 - communication cycle ................................ .......... - 38 - the instruction word (16 bits) ............................. - 39 - write ................................ ................................ .. - 39 - read ................................ ................................ .... - 40 - bus stalling in read/write a ccess ............... - 40 - msb/lsb first transfers ................................ .. - 41 - register map ................................ ........................... - 43 - reg ister map function descriptions ................. - 46 - serial port configuration ................................ ..... - 46 - pll configuration ................................ ................. - 47 - lvpecl outputs ................................ ................... - 56 - lvds/cmos outputs ................................ ............ - 58 - lvpecl channel dividers ................................ ...... - 60 - lvds/cmos channel dividers .............................. - 62 - vco divider and clk input ................................ ... - 64 - system ................................ ................................ . - 65 - update all registers ................................ ............ - 65 - package information ................................ ........... - 66 - m echanical data ................................ ......................... - 66 - m arking ................................ ................................ ..... - 66 -
AK8186B sep - 2012 draft - e - 02 - 4 - pin d escription pin configuration figure 2 . pin configuration top view 48 out6 /out6a 47 out6 /out6b 46 out7 /out7a 45 2 8 7 /out7b 44 gnd 43 out2 42 2 8 7 41 vdd_lvpecl 40 out3 39 out3 38 vdd 37 gnd 36 out9 /out9b 35 out9 /out9a 34 2 8 7 /out8b 33 out8 /out8a vdd 1 refmon 2 ld 3 vcp 4 cp 5 status 6 re f_sel 7 8 lf 9 bypass 10 vdd 11 vdd 12 clk 13 & |